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CY7C1347F
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
* Fully registered inputs and outputs for pipelined operation * 128K by 36 common I/O architecture * 3.3V core power supply * 2.5V/3.3V I/O operation * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 2.6 ns (for 225-MHz device) -- 2.8 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) -- 4.0 ns (for 133-MHz device) * User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * JEDEC-standard 100-pin TQFP, 119-pin BGA and 165-pin fBGA packages * "ZZ" Sleep Mode option and Stop Clock option * Available in Industrial and Commercial temperature ranges
Functional Description[1]
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250-MHz device) CY7C1347F supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC(R). The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.
Logic Block Diagram
A0, A1, A
ADDRESS REGISTER
2
A[1:0]
MODE ADV CLK
Q1
ADSC ADSP
BWD DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER
BURST COUNTER CLR AND Q0 LOGIC
DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE DRIVER
BWC
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE
GW CE1 CE2 CE3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05213 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 9, 2004
CY7C1347F
Selection Guide
-250 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 325 40 -225 2.6 290 40 -200 2.8 265 40 -166 3.5 240 40 -133 4.0 225 40 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
BYTE C
BYTE D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1347F
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
BYTE B
BYTE A
Document #: 38-05213 Rev. *D
MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1347F
Pin Configurations (continued)
119-Ball BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ
165-Ball fBGA
1 A B C D E F G H J K L M N P R
NC NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC NC
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC
NC
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05213 Rev. *D
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CY7C1347F
Pin Definitions
(BGA,FBGA)
Name
(100TQFP)
Name
I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous Input-Clock InputSynchronous InputSynchronous InputSynchronous
Description Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
A0,A1,A BWA,BWB, BWC,BWD GW
A[16:0] BW[A:D] GW
BWE CLK CE1 CE2 CE3 OE
BWE CLK CE1 CE2 CE3 OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputSynchronous InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ADV ADSP
ADV ADSP
ADSC
ADSC
InputSynchronous
ZZ
ZZ
InputZZ "sleep" Input. This active HIGH input places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed in a three-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Power supply for the I/O circuitry. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects.
DQA, DQB DQs DQPs DQC, DQD DQPA, DQPB, DQPC, DQPD VDD VSS VDDQ VSSQ MODE VDD VSS VDDQ VSSQ MODE
Power Supply Ground I/O Power Supply I/O Ground InputStatic
NC
NC
Document #: 38-05213 Rev. *D
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CY7C1347F
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (TCO) is 2.6 ns (250-MHz device). The CY7C1347F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[16:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[16:0] is loaded into the Address Register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs and DQPs inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and Document #: 38-05213 Rev. *D BW[A:D] signals. The CY7C1347F provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs and DQPs are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A[16:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs and DQPs is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs and DQPs are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1347F provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
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CY7C1347F
Interleaved Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00
Linear Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
Truth Table[2, 3, 4, 5, 6]
Next Cycle Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Snooze Mode, Power-down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H CE2 X L X L X X H H H H H X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L ADSP ADSC ADV WRITE X L X X L L H H X L L H H H H H X X H X H H X X X X L L X X X L L L H H H H H H H H H H X X X X X X X X X X L L L L L L H H H H X X X X X X X L H H H H H H L L H H H H OE X X X X X X L H X L H L H L H X X L H L H DQ CLK L-H three-state L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H three-state three-state three-state three-state three-state Q three-state D Q three-state Q three-state Q three-state D D Q three-state Q three-state
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05213 Rev. *D
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CY7C1347F
Truth Table[2, 3, 4, 5, 6]
Next Cycle Add. Used CE1 X H CE2 X X CE3 X X ZZ L L ADSP ADSC ADV WRITE H H H L X H H L OE X X CLK L-H L-H DQ D D
WRITE Cycle, Suspend Burst Current WRITE Cycle, Suspend Burst Current
Partial Truth Table for Read/write[2, 7]
Function Read Read Write Byte A - DQA Write Byte B - DQB Write Bytes B, A Write Byte C- DQC Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D- DQD Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Notes: 7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05213 Rev. *D
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CY7C1347F
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ........................................... -0.5V to VDD + 0.5V DC Input Voltage ....................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Com'l Ind'l Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V -5%/+10% VDDQ 2.5V -5% to VDD
Electrical Characteristics Over the Operating Range [8, 9]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[8] Voltage[8] VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -2.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input Load Current except ZZ and MODE GND VI VDDQ 2.0 1.7 -0.3 -0.3 -5 -30 5 -5 30 -5 4-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB1 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB2 All speeds Automatic CE Max. VDD, Device Deselected, Power-down VIN 0.3V or VIN > VDDQ - 0.3V, f Current--CMOS Inputs = 0 5 325 290 265 240 225 120 115 110 100 90 40 Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.7 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDDQ Input Current of ZZ IOZ IDD Input = VSS Input = VDDQ Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05213 Rev. *D
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CY7C1347F
Electrical Characteristics Over the Operating Range (continued)[8, 9]
Parameter ISB3 Description Test Conditions 4-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB4 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = 0 Min. Max. 105 100 95 85 75 45 Unit mA mA mA mA mA mA Automatic CE Max. VDD, Device Deselected, or Power-down VIN 0.3V or VIN > VDDQ - 0.3V Current--CMOS Inputs f = fMAX = 1/tCYC
Shaded areas contain advance information.
Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V TQFP Package 5 5 5 BGA Package 5 5 7 fBGA Package 5 5 7 Unit pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDDQ 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1ns
VL = 1.5V
1ns
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
(c)
R = 1667 VDDQ 5 pF GND R =1538 10%
ALL INPUT PULSES 90% 90% 10% 1ns
OUTPUT RL = 50 VL = 1.25V
(a)
INCLUDING JIG AND SCOPE
1ns
(b)
(c)
Thermal Resistance[10]
Parameter QJA QJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 41.83 9.99 BGA Package 47.63 11.71 fBGA Package 20.3 4.6 Unit C/W C/W
Note: 10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05213 Rev. *D
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CY7C1347F
Switching Characteristics Over the Operating Range[15, 16]
-250 Parameter tPOWER tCYC tCH tCL tAS tAH tCO tDOH tWES tWEH tALS tALH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Description VDD(min.) to the first access read or write [11] Clock Cycle Time Clock HIGH Clock LOW Address Set-up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise GW, BWS[3:0] Set-up Before CLK Rise GW, BWS[3:0] Hold After CLK Rise ADV/LD Set-up Before CLK Rise ADV/LD Hold after CLK Rise Data Input Set-up Before CLK Rise Data Input Hold After CLK Rise Chip Enable Set-up Before CLK Rise Chip Enable Hold After CLK Rise Clock to High-Z[12, 13, 14] Clock to Low-Z[12, 13, 14] OE HIGH to Output High-Z[12, 13, 14] OE LOW to Output Low-Z[12, 13, 14] OE LOW to Output Valid 0 2.6 0 2.6 0 2.6 1.0 0.8 0.4 0.8 0.4 0.8 0.4 0.8 0.4 2.6 0 2.6 0 2.8 Min. 1 4.0 1.7 1.7 0.8 0.4 2.6 1.0 1.2 0.5 1.2 0.5 1.2 0.5 1.2 0.5 2.6 0 2.8 0 3.5 Max. 1 4.4 2.0 2.0 1.2 0.5 2.6 1.0 1.2 0.5 1.2 0.5 1.2 0.5 1.2 0.5 2.8 0 3.5 0 4.5 -225 Min. Max. 1 5.0 2.0 2.0 1.2 0.5 2.8 2.0 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.5 0 4.0 -200 Min. Max. 1 6.0 2.5 2.5 1.5 0.5 3.5 2.0 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 4.0 -166 Min. Max. 1 7.5 3.0 3.0 1.5 0.5 4.0 -133 Min. Max. Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05213 Rev. *D
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CY7C1347F
Switching Waveforms
Read Cycle Timing[17]
t CYC
CLK
t CH t ADS t ADH
t CL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BW[A:D]
tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst.
tOEV t OEHZ t CLZ t OELZ tCO tDOH t CHZ
OE
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Single READ DON'T CARE UNDEFINED
BURST READ
Burst wraps around to its initial state
Notes: 17. On this diagram when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3is HIGH. 18. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05213 Rev. *D
Page 11 of 19
CY7C1347F
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
tCYC
CLK tCH tADS ADSP tADH tCL
ADSC tAS tAH
ADDRESS
A1
A2
A3 tWES tWEH
A4
A5
A6
BWE, BW[A:D] tCES CE tCEH
ADV
OE tCO tDS tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Document #: 38-05213 Rev. *D
Page 12 of 19
CY7C1347F
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
tCYC
CLK tCH tADS ADSP tADH tCL
ADSC tAS tAH
ADDRESS
A1
A2
A3 tWES tWEH
A4
A5
A6
BWE, BW[A:D] tCES CE tCEH
ADV
OE tCO tDS tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Note: 19. The data bus (Q)remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH
Document #: 38-05213 Rev. *D
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CY7C1347F
Switching Waveforms (continued)
ZZ Mode Timing [21, 22]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I SUPPLY
I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05213 Rev. *D
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CY7C1347F
Ordering Information
Speed (MHz) 250 225 200 Ordering Code CY7C1347F-250AC CY7C1347F-250BGC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-200AC CY7C1347F-200BGC CY7C1347F-200BZC CY7C1347F-200AI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166BGC CY7C1347F-166BZC CY7C1347F-166AI CY7C1347F-166BGI 133 CY7C1347F-133AC CY7C1347F-133BGC CY7C1347F-133BZC CY7C1347F-133AI CY7C1347F-133BGI Package Name A101 BG119 A101 BG119 A101 BG119 BB165C A101 BG119 A101 BG119 BB165C A101 BG119 A101 BG119 BB165C A101 BG119 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 165-Ball FBGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 165-Ball FBGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 165-Ball FBGA 100-Lead Thin Quad Flat Pack 119-Ball BGA Industrial Commercial Industrial Commercial Industrial Commercial Commercial Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05213 Rev. *D
Page 15 of 19
CY7C1347F
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05213 Rev. *D
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CY7C1347F
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05213 Rev. *D
Page 17 of 19
CY7C1347F
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.20 mm) BB165C
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7
PIN 1 CORNER
O0.25 M C A B O0.450.05(165X)
6 5 4 3 2 1
A B
A B
1.00
C D E F G
C D E F G
17.000.10
14.00
H J K
H J K
7.00
L M N P R
L M N P R
A
5.00 10.00
1.00
0.530.05
0.25 C
+0.05 -0.10
0.35
0.15 C
B 0.15(4X)
15.000.10
C 0.36
SEATING PLANE 1.40 MAX.
51-85165-*A
Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of International Business Machines, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05213 Rev. *D
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347F
Document History Page
Document Title: CY7C1347F 4-Mbit (128K x 36) Pipelined Sync SRAM Document Number: 38-05213 REV. ** *A *B *C ECN NO. Issue Date 119829 123117 127632 200660 12/16/02 01/18/03 06/13/03 See ECN Orig. of Change HGK RBI DPM SWI Description of Change New Data Sheet Added power-up requirements to AC test loads and waveforms information Final Data Sheet Improvements: Updated thermal resistance and capacitance Updated R5 pin of 119-Ball BGA from VDD to NC Updated all switching waveforms Clarifications: Updated footnotes Updated ZZ mode electrical characteristics Update Ordering Info section: Delete -100, shade -250, -225 Delete -100, Shade -250, -225 data from selection guide and characteristics
*D
213342
See ECN
VBL
Document #: 38-05213 Rev. *D
Page 19 of 19

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